In recent years, the density of components that are integrated into single integrated circuit devices has increased at a high rate. Examples of such high density circuits include dynamic random access memories (DRAMS) which are now being fabricated at 4 MBIT and 16 MBIT single chip densities. In order to accommodate such complexities, while maintaining the size of the chip at reasonable and manufacturable levels, the minimum feature size of transistors and other components of course must be reduced. For DRAM devices which have generally been most densely integrated device in the industry, the size of the feature such as MOS transistor gates is generally at the smallest size manufacturable by available technology. In the example of 16 MBIT DRAM devices, transistor gate lengths are expected to be within the range of 0.5 to 0.7 microns.
It is well known that MOS transistors, which have gate widths and accordingly transistor channel lengths, which are sub-micron dimensions, are subject to time and voltage dependent phenomena to which larger transistors are not subject. An example of such phenomena is transistor performance degradation due to hot-carder effects. While certain techniques are available to reduce the susceptibility of transistors to channel hot-carder effects, such as providing graded junction as described in U.S. Pat. No. 4,356,623, the drain to source voltage normally applied to the transistor structure remains a strong factor in the channel hot-carrier degradation of the transistor performance. Furthermore, the storage element of DRAMS is commonly a thin film capacitor, and it is well known that the data stored within the data DRAM capacitors may be upset by naturally occurring alpha particles. The degree to which data is lost in such events depends upon the capacitance of the memory cell, and accordingly, the capacitance of the modern DRAM cells is generally maintained above 35 fF for each cell and preferably above 50 fF. Since it is desirable that the density of storage cells per unit area should be as large as possible, in order to maintain the necessary storage capacity of 35 to 50 fF, the thickness of the capacitor dielectric must be reduced. Modern storage capacitors thus have the dielectric thickness on the order of the equivalent of 10 nm of silicon dioxide or less. However, with such thin capacitor dielectric, both dielectric breakdown voltage and time dependent dielectric breakdown rates degrade with thinner dielectrics, consuming a constant voltage applied across.
For these reasons, the power supply voltages across such high density VLSI devices including DRAMS, other memories and logic devices, are preferably reduced as the feature size decreases. In addition, since the power dissipation of the chip increases with increasing number of components integrated into the chip, a reduced power supply voltage will also reduce the device power dissipation. Many other circuits may still use the higher power supply voltages, for example 5 volts normally, then is desired by the high density components described above, for example, 3.3 volts, which makes the designer of systems incorporating these devices reluctant to provide an additional power supply to the system due to the cost of such other supplies and the routing of additional bias voltage.
It also should be noted that it is desirable that the performance of the integrated circuit should not vary strongly with the power supply voltage applied thereto. Such variation may increase the cost of production testing of the chip during its manufacture, but such variation may also cause system-level problems for the user.
Furthermore, in the field of DRAM devices, due to the large amount of thin capacitor dielectric on each device, manufacturing generally perform a "burn-in" operation during the test process of the chips. Burn-in is intended to stress the device, both by voltage and by temperature so that weak devices are removed from the population which is shipped to the user of the devices, for example, removing the "infant mortality" portion of the reliability curve. On chip regulation of the bias voltage for the memory array, for example will preclude the direct application of the power supply voltage to the capacitors. Hence, another means of providing the burn-in voltage to the capacitors must be provided. In order to determine when to apply such accelerated burn-in voltage to the capacitors, a burn-in detection circuit is also required in order to determine the switching of internal supply voltage.
FIG. 1 illustrates an example of burn-in detection circuits with a series of P-channel transistors 64, 66, 68 and 60 to detect the voltage, V.sub.DD, larger than N (where N is the number of P-channel transistors) times the threshold voltage of a P-channel transistor plus 3.3 volts. The circuit of FIG. 1 additionally has a feedback path through N-channel transistor 62 to provide hysteresis. During normal operations, when V.sub.DD is less than 3.3 volts plus N times the threshold voltage of a P-channel transistor, the trip point of the circuit, none of the P-channel transistor in series is turned on to conduct current. Hence N-channel transistor 70 is able to discharge node 50 to low and maintain its state. As node 50 is at logically low state, BINEN.sub.-- is high and BINEN is low. Thus, N-channel transistor 62 is also turned on to further maintain node 50 at low state. In burn-in test mode, when Vdd is raised sufficiently above the trip point, the conduction current through the seriesly connected P-channel transistors becomes large enough to overdrive the conduction currents generated by N-channel transistors 70 and 62 to charge node 50 higher to invert the states of signals BINEN.sub.-- and BINEN. As node BINEN.sub.-- is inverted from high to low during burn-in test operation, N-channel transistor 62 is turned off, hence reducing the pull down current at node 50. As a result, the trip point for returning to normal node is slightly changed, hence a hysteresis is generated. The circuit of FIG. 1 is sensitive to variations of the threshold voltage due to nonuniformity introduced in the manufacturing phase and due to ambient temperature change. Furthermore, the variations of the threshold voltage for P-channel transistors 64, 66, 68 and 60 are multiplied by N where N is the number in the series of transistors. Since a burn-in detection circuit needs to operate over a wide range of temperatures and with good manufacturing tolerances, the approach of FIG. 1 is inadequate to meet all the needs of the user.